1. Field of the Invention
The present invention relates to fabrication of devices having accurately formed designed features on small scales.
2. Discussion of the Background
The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography, or simply lithography. As is well known, lithographic processes can be used to transfer a pattern of a photomask (also referred to as a “reticle”) to a wafer. Patterns can be formed from a photoresist layer disposed on the wafer by passing light energy through the photomask mask to form an image of the desired pattern onto the photoresist layer. As a result, the pattern is transferred to the photoresist layer. In areas where the photoresist is sufficiently exposed, after a development cycle the photoresist material can become soluble such that it can be removed to selectively expose an underlying layer (e.g., a semiconductor layer, a non-semiconductor layer, a metal or metal containing layer, a dielectric layer, a hard mask layer, etc.). Portions of the photoresist layer not exposed to a threshold amount of light energy will not be removed and will serve to protect the underlying layer during further processing of the wafer (e.g., etching exposed portions of the underlying layer, implanting ions into the wafer, etc.). Thereafter, the remaining portions of the photoresist layer can be removed.
There is a continuing objective to increase the density with which various integrated circuit structures are arranged. To this end feature size, line width, and the separation between features and lines are becoming increasingly smaller. Fabrication in the sub-micron range incurs limitations in faithfully reproducing reticle patterns as exposed images on the photoresist layer. Yield is affected by factors such as mask pattern fidelity, optical proximity effects and photoresist processing.
Nodes with a critical dimension of about 32 nanometers (nm) to about 65 nm have been proposed, and in the future 22 nm or below may be needed. In these sub-micron processes, yield is affected by factors such as mask pattern fidelity, optical proximity effects and photoresist processing. These concerns are largely dependent on local pattern density and topology. For example, for a repetitive line pattern, a minimum printable pitch for a single exposure of the photoresist through the mask reticle can be determined. That is, a pitch smaller than the minimum pitch will produce an unacceptable exposure pattern.
One approach for overcoming such problems has been to employ two photoresist layers each subjected to exposure through a reticle. For example, a first resist pattern is formed over a target layer and then the resist pattern may be covered by a cover layer. A second resist pattern can then be formed on the cover layer over the first resist pattern leaving exposed portions of the cover layer. The cover layer can then be selectively etched to remove the exposed portions of the cover layer. A target pattern is defined by the first and second resist patterns. The target pattern may be used as a mask for etching the target layer. However, such a double exposure technique presents difficulties in appropriately overlaying the various layers with each other and with the one or more patterned masks that may be required.
Thus, the need exists to develop a process for forming devices with smaller feature sizes, without the drawbacks and problems associated with the processes discussed above.